The present invention relates to an image processing apparatus that divides image data into a plurality of blocks for processing, particularly to a technique of storing image data in discontinuous memory regions, further to a technique of DMA (Direct Memory Access) transfer of image data between a plurality of memory regions and a storage device.
In an image processing apparatus such as a photocopier that handles image data in units of page, the one-page image data having been read is normally stored in a continuous memory region, with consideration given to processing ease and processing speed.
In one of the image processing apparatuses having been disclosed, to ensure high speed compression/expansion of the image data, one-page image data is divided into a plurality of regions, and a separate compression/expansion device is provided for each region to perform processing (e.g., Unexamined Japanese Patent Application Publication No. 5-91341).
A technique for DMA (Direct Memory Access) transfer of the divided image data to a memory or the like is disclosed in the information processing apparatus, wherein a CPU (Central Processing Unit) produces the descriptor information wherein the information (e.g., start address and number of transfer bites) required for DMA transfer of one divided region is described in a line for a plurality of divided regions. The DMA controller refers to this descriptor information sequentially from the leading edge, and sequentially executes a plurality of DMA transfer steps (e.g., Unexamined Japanese Patent Application Publication No. 2002-140286). In this apparatus, a plurality of DMA transfer steps are automatically carried out by the DMA controller according to the descriptor information. This eliminates the possibility of an interrupt occurring to the CPU at every completion of the DMA transfer for each divided region, and reduces CPU processing loads.
In another technique that has been disclosed, when two DMA controllers (e.g., data write/read side) accesses one and the same memory, a pause bit is incorporated in the descriptor information referred to by the DMA controller and the transfer operation is suspended temporarily, so that the alternate operation of two DMA controllers is performed (e.g., Unexamined Japanese Patent Application Publication No. 2003-281078).
In the method of storing one-page image data in a continuous memory region, even if the size requirements can be satisfied when all the vacant regions are added together, processing cannot be started until one continuous region is obtained. This has reduced the productivity of the apparatus. For example, when a system memory is shared by the work area for execution of software and the image data storage region, the memory region tends to be fragmented due to the differences in the size of the region to be used or the time of releasing. This makes it difficult to ensure a large continuous region for image data storage (e.g., about 4M-byte region for A4-sized monochromatic sheet).
In the meantime, if arrangement is made in such a way that a continuous region stays resident for the exclusive purpose of image data storage, then a memory region for the maximum page size and the minimum compression rate must stay resident. This structure will reduce the utilization efficiency.
In the aforementioned technique disclosed in the Unexamined Japanese Patent Application Publication No. 5-91341, image data is divided into a plurality of regions, and a process of compression/expansion is applied to each of the divided regions. However, the compressed image data must be stored in the continuous region in the final stage. Thus, this technique also fails to solve the aforementioned problem.
The method of using descriptor information for DMA transfer of the divided image data into a memory or the like is effective to reduce the CPU load. However, the conventional descriptor information is designed for sequential execution of a plurality of DMA transfer steps by one DMA channel or is built to perform alternate operation of two DMA controllers. Thus, such a conventional method fails to provide effective transfer of the image data divided into a plurality of blocks through simultaneous and parallel operation of a plurality of DMA channels.
The object of the present invention is to solve the aforementioned problems and to provide an image processing apparatus capable of storing the divided image data into discrete vacant regions, and an image processing apparatus capable of effective transfer of the divided image data using a plurality of DMA channels.
Incidentally, to store a large amount of image data, the image data stored in the memory is compressed, and is transferred and stored in a storage device such as a hard disk apparatus. For example, the image data outputted from the compressor is once re-stored in a buffer region in the memory, and the image data is then DMA-transferred from this buffer region to the hard disk apparatus.
Further, in an image processing apparatus (e.g., Unexamined Japanese Patent Application Publication No. 2003-179732), one-page image data is divided into a plurality of blocks, and DMA transfer of the image data from the memory to the hard disk apparatus is carried out for each division. In another image processing apparatus (e.g., Unexamined Japanese Patent Application Publication No. 2003-198815), the amount of DMA transfer for each operation and the size of the buffer region are controlled in response to the size of the continuous region that can be stored in a hard disk apparatus.
As described above, when a plurality of DMA transfer steps are to be performed, a DMA descriptor table is utilized in order to reduce the processing load of the CPU1 (Central Processing Unit) resulting from the interrupt occurring for each completion of the DMA transfer. The DMA descriptor table contains the DMA transfer start address and number of transfer bites described in a line for a required number of operation steps. The CPU produces a DMA descriptor table, and the DMA controller refers to this DMA descriptor table sequentially from the leading edge so that a plurality of DMA transfer steps are executed sequentially in an automatic mode.
In the method of storing one-page image data in a continuous memory region, even if the size requirements can be satisfied when all the vacant regions are added together, processing cannot be started until one continuous region is obtained. This has reduced the productivity of the apparatus. For example, when a system memory is shared by the work area for execution of software and the image data storage region, the memory region tends to be fragmented due to the differences in the size of the region to be used or the time of releasing. This makes it difficult to ensure a large continuous region for image data storage (e.g., about 4M-byte region for A4-sized monochromatic sheet).
In the meantime, if arrangement is made in such a way that a continuous region stays resident for the exclusive purpose of image data storage, then a memory region for the maximum page size and the minimum compression rate must stay resident. This structure will reduce the utilization efficiency.
It will be beneficial if image data is stored in the discrete memory regions present in the system memory. However, collective management of all the information on the head address and size of these memory regions is essential to store image data in a plurality of discrete memory regions.
When the DMA transfer of the image data of the discrete memory regions into a hard disk apparatus or the like is to be performed, the transfer operation must be separated into several steps. Thus, the DMA descriptor table is preferably employed.
This requires creation of a DMA descriptor table as well as the information for the management of a plurality of discrete memory regions present in the CPU. This will increase the CPU processing loads for the creation of such data, as well as the memory size to store such information, with the result that memory utilization efficiency is reduced.
The second object of the present invention is to solve these problems and to provide an image processing apparatus which, using a plurality of discrete memory regions, can reduce CPU processing loads involved in producing the administrating information for storage of image data, and the administrating information for DMA transfer of image data between a plurality of memory regions and storage device, as well as the memory size for storing such administrating information.